Responsibilities include (but not limited to):
- RTL and integration including RTL coding, RTL checkers, SDC, timing collaterals, Sector integration and Routing channel design
- RTL Coding: Develop high-quality RTL code for digital circuits, adhering to design specifications, coding standards, and performance requirements.
- Timing Analysis: Perform static timing analysis (STA) to ensure that the design meets timing constraints and identify potential issues.
- SDC Creation: Develop Static Design Constraints (SDC) to define the timing requirements and constraints for the design.
- Timing Characterization: Analyze and characterize the timing behaviour of the design to ensure it meets performance targets.
- Integration: Integrate the designed circuits into larger systems, ensuring compatibility and proper functionality.
- Linting and CDC: Conduct linting and clock domain crossing (CDC) analysis to identify and address potential design issues.
- Test and Release: Participate in the testing and release process of the design, ensuring it meets quality standards and is ready for production.
Minimum Qualifications:
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- Strong understanding of digital circuit design principles and methodologies.
- Proficiency in Verilog or VHDL.
- Experience with design verification tools and methodologies.
- Knowledge of timing analysis tools and techniques.
- Familiarity with scripting languages (e.g., Python, Perl).
- Excellent problem-solving and analytical skills.
- Ability to work independently and as part of a team.
