Verilog Jobs

CPU System Validation Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

RTL simulation Ip RISC-V C/C++ Scripting Language Assembly Language Cpu Perl X86 Arm System Verilog Python

4 days ago

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

2-10 years

hardware validation HDL score Uvm Verdi/DVE Synopsys VCS Axi AMBA Surecov Graphics AHB Unix Usb Networking C++ Ovm Cpu Pcie Perl Ethernet Debugging Arm System Verilog Python

4 days ago

Senior SoC Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-7 years

IO Controller SOC design Hardware Emulation Memory Design Functional Safety Design Constraint Axi rtl verification HBM D2D CXL APB Interface ASIC Design EDA Tools AMBA Bus Architecture AHB Rtl Design LPDDR5 DDR Pcie Verilog Ethernet System Verilog

5 days ago

RTL Logic Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

RTL Sector Analysis Team Circuits Test analytical Tools Languages Problem-solving Channel checkers linting static Verification Timing Digital Independent behaviour cdc Design VHDL collaterals SDC Methodologies Coding Scripting Release Verilog Integration Perl Performance Constraints Routing Python

3 days ago

Component Debug Engineering Manager

Permanent Job

Penang ,

Malaysia

1-7 years

VHDL Vlsi ASIC Ate Digital Design PERL Verilog Jtag Python Computer Architecture

6 days ago

Digital IC Design Engineer / Senior / Principle

Permanent Job

Penang

2-10 years

Confidential

Sta Place & Route Design Compiler primetime RTL low power design Synthesis Dft VHDL ASIC Fpga C C++ PERL Verilog Static Timing Analysis Matlab

10 days ago

FPGA Design System Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

QDR-IV Microchip Libero AXI-4 system Verilog RTL coding Siemens Questasim QDR-II PCB design tools AMD-Vivado AHB Spi Verilog I2c

12 days ago

AI IP & System Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-7 years

Whitebox FPGA IDE tool RTL logic design English communication skill hardware description language Verilog System Verilog

12 days ago

Mixed Signal Verification

Permanent Job

Penang ,

Malaysia

5-7 years

AMS verification verilog-AMS Questa Synopsys virtuoso schematic editor Simulators EDA Tools Customsim Xcelium Cadence Eldo Xps VerilogA Siemens analog circuits Vcs Verilog Aps

12 days ago

Staff/ Senior SOC Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Synthesis RTL digital circuit design script language clock/reset structure Verification peripheral IO timing signoff SDIO micro-architectures Eda Uart Soc Spi Verilog

17 days ago

Digital IC Design Engineer

Permanent Job

Penang ,

Malaysia

Fresher

Sta Synthesis Dft RTL C/C++ Fpga Verilog

25 days ago

AI Hardware Development Enginner

Permanent Job

Malaysia ,

Kuala Lumpur

1-3 years

Signal Processing project management GPUs Simulation Tools AI applications Analytical Skills industry-standard hardware design FPGAs Problem-solving VHDL hardware description languages Embedded Systems Hardware Design TPUs digital and analog circuit design communication custom AI chips Verilog

29 days ago

Mixed Signal Verification Engineer

Permanent Job

Malaysia ,

Kuching ,

Sarawak

0-2 years

ISO26262 Functional Safety Uvm IEC61508 Verilog-AMS Verilog-A Git Shell PERL Verilog Gitlab System Verilog Python

27 days ago

Analog Design Engineer

Permanent Job

Malaysia ,

Kuching ,

Sarawak

5-7 years

device parasitics stability analysis analog block designs written and oral communications skills Technical CMOS process Cadence noise analysis LDO regulators feedback analysis Responsibility EDA Tools Siemens VCOs design rules Comparators 6-sigma design practices DRC/LVS/ERC engineering tasks verification procedures Simulation Models solution driven self-motivated English Amplifiers bandgap voltage references Synopsys Verilog A/AMS modelling Statistical Analysis

27 days ago

Intern - Physical Design

Permanent Job

Penang ,

Malaysia

0-2 years

silicon process technology Verbal Communication RTL timing requirement Physical Design Problem Solving Analytical Skills VHDL Written Communication Verilog Debugging Scripting

a month ago

Senior SOC Design Engineer

Permanent Job

Bayan ,

Malaysia

5-7 years

cpu design MMU DDR Eda Cache python Perl Verilog Tcl

30 days ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

30 days ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

30 days ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Lead I - Embedded Hardware

Permanent Job

Bayan ,

Malaysia

0-2 years

power management Schematics Memory VHDL ASIC PC Architecture Power interfaces communication Team Work Documentation memory controllers Speed power delivery systemverilog Software Programming Schematic Allegro Design Entry HDL Allegro PCB Designer HSIO busses Simulation Fpga test automation Verilog intel architecture Debugging Digital Signal Processing Scripting Programming Language Logic Design

30 days ago

SOC Design Engineering Graduate Trainee

Permanent Job

Kedah ,

Kulim ,

Malaysia

0-2 years

analytical debug skills validation methodologies RTL integration communication Verilog C Programming UNIX

5 months ago

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Debug Uvm systemverilog digital simulation assembly DDR protocols C/C++ Noc Cpu Perl Pcie Verilog Ethernet Python

5 months ago

FPGA Engineer

Permanent Job

Malaysia

0-2 years

quartus VHDL Vivado Xilinx Ise Fpga Verilog

5 months ago

Logic Design Engineer

Permanent Job

Penang ,

Malaysia

3-4 years

cdc LINT RTL ip design Power UPF UCIe systemverilog primetime Synthesis HBM Auto P and R SOC integration mixed signal designs DDR Pcie Verilog Static Timing Analysis analog circuits

5 months ago

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Verilog Jobs

CPU System Validation Engineer

Design Verification Engineer

Senior SoC Design Engineer

RTL Logic Design Engineer

Component Debug Engineering Manager

Digital IC Design Engineer / Senior / Principle

FPGA Design System Engineer

AI IP & System Engineer

Mixed Signal Verification

Staff/ Senior SOC Design Engineer

Digital IC Design Engineer

AI Hardware Development Enginner

Mixed Signal Verification Engineer

Analog Design Engineer

Intern - Physical Design

Senior SOC Design Engineer

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (IP Design Verification)

Associate III - VLSI (DFT)

Associate III - VLSI (STA)

Lead I - Embedded Hardware

SOC Design Engineering Graduate Trainee

Design Verification Engineer

FPGA Engineer

Logic Design Engineer

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