Rtl Jobs

RTL Logic Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

RTL Sector Analysis Team Circuits Test analytical Tools Languages Problem-solving Channel checkers linting static Verification Timing Digital Independent behaviour cdc Design VHDL collaterals SDC Methodologies Coding Scripting Release Verilog Integration Perl Performance Constraints Routing Python

7 days ago

Digital IC Design Engineer / Senior / Principle

Permanent Job

Penang

2-10 years

Confidential

Sta Place & Route Design Compiler primetime RTL low power design Synthesis Dft VHDL ASIC Fpga C C++ PERL Verilog Static Timing Analysis Matlab

a day ago

RTL | Digital Design Engineer

Permanent Job

Bayan ,

Malaysia

0-2 years

CHI Mixed signals SoCs Low-power UPF Security high-performance techniques Display port power management Architecture Functional safety SoCs Clock Domain Crossing (CDC) Axi MIPI Micro-architecture coherency Low Power AHB Booting/Reset Flow DDR Pcie PERL Shell scripting Python Usb Nvme Ethernet Tcl

a month ago

CPU System Validation Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

RTL simulation Ip RISC-V C/C++ Scripting Language Assembly Language Cpu Perl X86 Arm System Verilog Python

7 days ago

Senior SoC Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-7 years

IO Controller SOC design Hardware Emulation Memory Design Functional Safety Design Constraint Axi rtl verification HBM D2D CXL APB Interface ASIC Design EDA Tools AMBA Bus Architecture AHB Rtl Design LPDDR5 DDR Pcie Verilog Ethernet System Verilog

9 days ago

Staff/ Senior SOC Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Synthesis RTL digital circuit design script language clock/reset structure Verification peripheral IO timing signoff SDIO micro-architectures Eda Uart Soc Spi Verilog

20 days ago

FPGA Design System Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

QDR-IV Microchip Libero AXI-4 system Verilog RTL coding Siemens Questasim QDR-II PCB design tools AMD-Vivado AHB Spi Verilog I2c

16 days ago

AI IP & System Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-7 years

Whitebox FPGA IDE tool RTL logic design English communication skill hardware description language Verilog System Verilog

16 days ago

Digital IC Design Engineer

Permanent Job

Penang ,

Malaysia

Fresher

Sta Synthesis Dft RTL C/C++ Fpga Verilog

29 days ago

Intern - Physical Design

Permanent Job

Penang ,

Malaysia

0-2 years

silicon process technology Verbal Communication RTL timing requirement Physical Design Problem Solving Analytical Skills VHDL Written Communication Verilog Debugging Scripting

a month ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

a month ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

a month ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

a month ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

a month ago

SMT QA Engineer

Permanent Job

Senai ,

Malaysia

3-5 years

IPC standard x-ray machine capability studies bahasa malaysia customer complaint First Article part RTL customer audit OBA customer line acceptance approval Leadership Quality Improvement Customer Satisfaction Doa PCBA quality issue Verification ISO9000 quality management system Inspection Communication Skills rma product specification line qualification approval CAPA action English Failure Analysis ESD compliance activities Chinese Ncr Components Qa

a month ago

SOC Design Engineering Graduate Trainee

Permanent Job

Kedah ,

Kulim ,

Malaysia

0-2 years

analytical debug skills validation methodologies RTL integration communication Verilog C Programming UNIX

5 months ago

Logic Design Engineer

Permanent Job

Penang ,

Malaysia

3-4 years

cdc LINT RTL ip design Power UPF UCIe systemverilog primetime Synthesis HBM Auto P and R SOC integration mixed signal designs DDR Pcie Verilog Static Timing Analysis analog circuits

5 months ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Logic Synthesis Reliability RTL physical clock design Physical Design Dft ASIC Gds EDA Tools Structural Design automated place and route tools Synthesis coverage analysis VLSI circuits Place And Route power and noise analysis design techniques Logic equivalent verification debugging sub-micron CMOS technologies Floor Planning power/clock distribution Timing Closure multiple power domain analysis Testchip Logic design fundamentals Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

Design Enablement Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

Design Technology Co-Optimization Si Validation Foundational IPs Digital Computer Science RTL STEM Gds Process Design Kits Electrical Engineering Design Flow Eda Perl Analog Python Computer Engineering Tcl

5 months ago

Staff, Digital Design Engineer

Permanent Job

Penang ,

Malaysia

10-12 years

ASIC RTL Fpga Tcl/Tk System Verilog Python

5 months ago

Customer Engineering: System Design Engineer

Permanent Job

Penang ,

Malaysia

2-4 years

Circuit area PFR solutions SoCs RISC-V systems FPGAs Rtl Design ASICs English Communication Skills Problem Solver architecture Power Microarchitecture Creative Thinker Usb Spi Performance system integration I2c

3 months ago

Software Development Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

RTL Memory DDR C/C++ Serdes interface Fpga Tcl Ethernet Python Perl Pcie

5 months ago

SW Dev Eng 2

Permanent Job

Penang ,

Malaysia

4-6 years

EDA SW Tool development Serdes interface RTL C/C++ Memory DDR Fpga Perl Pcie Ethernet Python Tcl

5 months ago

SW Dev Eng 4

Permanent Job

Penang ,

Malaysia

8-10 years

Rtl Design Simulation graph algorithms Data Structure C++ Perl Verilog Python

5 months ago

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rtl Jobs

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Rtl Jobs

RTL Logic Design Engineer

Digital IC Design Engineer / Senior / Principle

RTL | Digital Design Engineer

CPU System Validation Engineer

Senior SoC Design Engineer

Staff/ Senior SOC Design Engineer

FPGA Design System Engineer

AI IP & System Engineer

Digital IC Design Engineer

Intern - Physical Design

Physical Design Engineer

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (IP Design Verification)

Associate III - VLSI (DFT)

Associate III - VLSI (STA)

SMT QA Engineer

SOC Design Engineering Graduate Trainee

Logic Design Engineer

Physical Design Engineer

Design Enablement Graduate Trainee

Staff, Digital Design Engineer

Customer Engineering: System Design Engineer

Software Development Engineer

SW Dev Eng 2

SW Dev Eng 4