Physical Design Engineer

Responsibility

Responsible for high performance block implementation (RTL to GDSII).

Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing.

Close the design to meet timing, power budget and area targets.

Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements.

Implement ECO's to address functional bugs, timing and physical verification violations.

Responsible for generation and maintenance of block level STA constraints and perform STA signoff checks.

Responsible for timing model generation and support successful integration of blocks into SOC.

Qualification

3-5 years of hands-on experience in digital physical design.

Master's/Bachelor's degree in Electrical Engineering with an emphasis in IC design

Experience in floor planning and routing

Good experience with Synopsys implementation tools (DC, ICC2), experience with Cadence (Innovus) implementation tool is a plus.

Experience with Static Timing Analysis and Synopsys primeTime

Experience in Mentor Verification tool, Calibre

Experience in advanced process nodes (5nm) is preferred

Proficient in TCL coding, Perl/Python knowledge is a plus

Good written and communication skills