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13
Lvs Jobs
Layout Engineer - Mask Design (Staff or Senior Staff Engineer)
JobsJK PLT
Permanent Job
Penang
5-12 years
Confidential
Vlsi
Tapeout
CAD
Cadence
LVS
Calibre
ASIC
Layout
DRC
PDK
virtuoso
Mask Design
a day ago
Network Security Engineer (Mandarin Speaker) RM 8,000 - RM 20,000
Agensi Pekerjaan Intho Sdn Bhd
Permanent Job
Malaysia
,
Kuala Lumpur
7-9 years
information security assessment
Security Operations
vulnerability libraries
security assessment
anti-crawling
defense technologies
IDC
gateway security
SLB
LVS
technical architectures
vulnerability information
Security
security trends
knowledge bases
cloud security issues
container security
Security Design
anti-crawl defense
enterprise-level information systems
host security
zero-trust system construction
attack behaviors
cutting-edge attack
security reinforcement
container network
traffic security
nids
attack and defense tool libraries
security construction
HIDS
Network Components
edge network
hybrid cloud
anti-DDOS
network security expertise
security auditing technology
Nat
Encryption
Nginx
Public Cloud
Sdp
SDWAN
virtualization
Firewall
Waf
3 days ago
Analog Layout Designer
CONNEXUS
Permanent Job
Penang
,
Bayan
,
Malaysia
0-2 years
Mentor Calibre DRC/LVS/ERC
Circuit
schematic-driven layout
chip level routing
Independent
design rule
Trouble Shooting
high-speed signals layout techniques
critical device matching
CAD Tools
Analysis
self-motivated
Floor Planning
Responsibility
urgency
physical design verifications
mixed-signal
Team Spirit
creative problem solver
Analog
8 days ago
Staff Engineer - EDA & CAD Support
Infineon Technologies
Permanent Job
Penang
,
Malaysia
5-7 years
Analog Mixed Signal
transistor-level simulation
layout editor
LVS/DRC
Cadence schematic
Perl/Python
Hspice
cadence spectre
16 days ago
Analog Design Engineer
SMD Semiconductor
Permanent Job
Malaysia
,
Kuching
,
Sarawak
5-7 years
device parasitics
stability analysis
analog block designs
written and oral communications skills
Technical
CMOS process
Cadence
noise analysis
LDO regulators
feedback analysis
Responsibility
EDA Tools
Siemens
VCOs
design rules
Comparators
6-sigma design practices
DRC/LVS/ERC
engineering tasks
verification procedures
Simulation Models
solution driven
self-motivated
English
Amplifiers
bandgap voltage references
Synopsys
Verilog A/AMS modelling
Statistical Analysis
a month ago
Senior Network Security Engineer (INT05082024-4)
Agensi Pekerjaan INTHO SDN BHD
Permanent Job
Malaysia
,
Kuala Lumpur
7-9 years
information security assessment
Security Operations
vulnerability libraries
security assessment
zero-trust system
anti-crawling
defense technologies
gateway security
SLB
LVS
technical architectures
vulnerability information
Security
security trends
knowledge bases
cloud security issues
container security
Security Design
anti-crawl defense
enterprise-level information systems
host security
Security Products
attack behaviors
cutting-edge attack
security reinforcement
container network
traffic security
nids
attack and defense tool libraries
HIDS
Network Components
edge network
anti-DDOS
network security expertise
security auditing technology
Nat
Encryption
Nginx
Sdp
SDWAN
virtualization
Firewall
Waf
a month ago
STA/PnR/InR/Synthesis Engineer
UST Malaysia
Permanent Job
Penang
,
Malaysia
4-6 years
tempus
innovus
ir analysis
power switches
power grid development
dynamic ir
ERC
drc
rtl2n
multi-voltage
Sta
Synthesis
static
power/signal em
calibre
em
Ir
LVS
Dfm
Physical Verification
multi-power domain
PNR
Esd
Timing Closure
irdrop
Soc
Clp
Ant
a month ago
Test Chip Engineering Manager
Intel Corporation
Permanent Job
Penang
,
Malaysia
5-10 years
Physical Design
fill code
LVS
Routing code
gpds
Calibre
python OA
ICV
layout editing
Extraction
verification CAD tools
Skill
automation
programming
Gui Development
5 months ago
E-core CPU Senior Physical Design Engineer
Intel Corporation
Permanent Job
Penang
,
Malaysia
0-8 years
APR flows
primetime
Noise
Fusion Compiler
cross-talk
ICC2
Conformal
Physical Design
electro-migration checks
Calibre
Synthesis
Layout physical design
Formal equivalence
redhawk
Dce
StarRCXT
Ir
DRC/LVS
OCV analysis
Timing Verification
Timing Closure
DCT
ICV
Cpu
Soc
Tcl Scripting
5 months ago
PDK Development Graduate Trainee
Intel Corporation
Permanent Job
Penang
,
Malaysia
0-2 years
layout verification software
Layout of analog
LVS
test-cases development
parasitic
2D and 3D electromagnetic packages
validation of Process Design Kit (PDK) collaterals
Extraction runset and flow development
Automation Software
Technology file development
popular extraction solutions
industry standard CAD tools
analysis of CAD tool results
CAD
Custom Layout tools
interconnects
Digital Circuits
rc extraction
electromagnetic packages
Rf
DRC
QA plans
solvers
schematic entry
Unix
Eda
Python
Analog
Perl
Linux
Tcl
5 months ago
E-core CPU Physical Design Engineer
Intel Corporation
Permanent Job
Penang
,
Malaysia
0-5 years
APR flows
primetime
Noise
Fusion Compiler
cross-talk
ICC2
Conformal
Physical Design
electro-migration checks
Calibre
Synthesis
Layout physical design
Formal equivalence
redhawk
Dce
StarRCXT
Ir
DRC/LVS
OCV analysis
Timing Verification
Timing Closure
DCT
ICV
Cpu
Soc
Tcl Scripting
5 months ago
E-core CPU Physical Design Engineer
Intel Corporation
Permanent Job
Penang
,
Malaysia
0-5 years
APR flows
primetime
Noise
Fusion Compiler
cross-talk
ICC2
Conformal
Physical Design
electro-migration checks
Calibre
Synthesis
Layout physical design
Formal equivalence
redhawk
Dce
StarRCXT
Ir
DRC/LVS
OCV analysis
Timing Verification
Timing Closure
DCT
ICV
Cpu
Soc
Tcl Scripting
5 months ago
Senior Backend Physical Verification Engineer Leader
TalentWork
Permanent Job
Penang
,
Malaysia
,
George Town
5-7 years
EDA Tools
DRC
Antenna
EM
LVS
Physical Verification
backend notation
Perl
Python
Tcl
4 months ago
1
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