Experience: 5+ years of experience in Analog & mixed signal verification domain
Working location: Penang, Malaysia
Responsibilities:
- Mixed signal verification engineers responsible for AMS verification
- Development of AMS test plan and checkers or SV assertions.
- Behavioral model development for analog blocks using Verilog/Verilog-A/Verilog-AMS.
- Functional coverage closure.
Requirements
- 5+ years of experience in Analog & mixed signal verification domain.
- Good understanding of analog circuits and ability to write behavioral models using verilog/verilogA/verilog-AMS.
- Ability to develop AMS test plan, implement TB components, integrate spice netlists, develop checkers, assertions, coverage, and debugging AMS simulations.
- Interact with Analog, RTL & DV teams to bring up system level scenarios in AMS environment.
- Efficient working knowledge on EDA tools/simulators (Cadence - virtuoso schematic editor, Xcelium,APS/XPS OR Synopsys VCS, Customsim OR Siemens - Questa, Eldo).
- Self-motivated to work effectively & should be able to handle work independently.
Contact Ms. Anna - WhatsApp: +84935059669
Email: [Confidential Information]
