Synopsys Jobs

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

2-10 years

hardware validation HDL score Uvm Verdi/DVE Synopsys VCS Axi AMBA Surecov Graphics AHB Unix Usb Networking C++ Ovm Cpu Pcie Perl Ethernet Debugging Arm System Verilog Python

4 days ago

Mixed Signal Verification

Permanent Job

Penang ,

Malaysia

5-7 years

AMS verification verilog-AMS Questa Synopsys virtuoso schematic editor Simulators EDA Tools Customsim Xcelium Cadence Eldo Xps VerilogA Siemens analog circuits Vcs Verilog Aps

13 days ago

Applications Engineering, Engineer

Permanent Job

Penang ,

Malaysia

1-3 years

Signoff primetime Fusion Compiler Formality PrimeClosure RTL2GDS PNR EDA Tools scripting skills Functional Verification advanced process nodes Perl Python Tcl

a month ago

Analog Design Engineer

Permanent Job

Malaysia ,

Kuching ,

Sarawak

5-7 years

device parasitics stability analysis analog block designs written and oral communications skills Technical CMOS process Cadence noise analysis LDO regulators feedback analysis Responsibility EDA Tools Siemens VCOs design rules Comparators 6-sigma design practices DRC/LVS/ERC engineering tasks verification procedures Simulation Models solution driven self-motivated English Amplifiers bandgap voltage references Synopsys Verilog A/AMS modelling Statistical Analysis

27 days ago

Senior SIPI Lead Engineer, Hardware Design

Permanent Job

Penang ,

Malaysia

3-5 years

TDR Sigrity Power SI Transmission-line S-parameters Electromagnetic DDR3/4 Cst Microwave Studio VNA Mentor ICX ANSYS HFSS Keysight ADS 25G/56G Ethernet Synopsys HSPICE Cadence SPECCTRAQuest SiSoft SI-Auditor SAS VB Perl Pcie Matlab Python

26 days ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

30 days ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

30 days ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago

Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

Power Distribution 3D passive channel modeling Electromagnetic Pcb Design ANSYS HFSS Keysight ADS 25G/56G Ethernet specification Synopsys HSPICE 3-D field solver ASIC SerDes channel extraction S-parameters theory parallel interfaces VNA measurements power integrity analysis stack-up definition TDR Sigrity Power SI MSEE Transmission-line DDR3/4 Mentor ICX Cst Microwave Studio multi-gigabit serial links BSEE SerDes design Pcb Signal Integrity PCB layout rules Written Communication Oral Communication Cadence SPECCTRAQuest SiSoft SI-Auditor SAS Pcie Python VB Perl Matlab

a month ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Sta Dc CTS Synopsys implementation tools ICC2 Mentor Verification tool RTL timing optimization physical verification flows Cadence LVS written communication skills Innovus Calibre power grid implementation APR placement advanced process nodes EM Ir Floor Planning Eco TCL coding DRC synopsys primetime GDSII routing Static Timing Analysis Python Perl

5 months ago

Product Yield Engineer

Permanent Job

Penang ,

Malaysia

5-6 years

test manufacturing ATE tester Synopsys Yield Explorer wafer sort Final Test Design for Test silicon sort Testability Requirements Jmp

5 months ago

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Synopsys Jobs

Design Verification Engineer

Mixed Signal Verification

Applications Engineering, Engineer

Analog Design Engineer

Senior SIPI Lead Engineer, Hardware Design

Associate III - VLSI (IP Design Verification)

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (STA)

Associate III - VLSI (DFT)

Physical Design Engineer

Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)

Physical Design Engineer

Product Yield Engineer