Job Position: Design Verification Engineers
Location: Penang, Malaysia
Job Responsibilities
- SoC/IP verification experience using OVM/UVM methodology and System Verilog with more than 2 years of experience.
- Recent work experience includes working on test cases creation, test benches and building environment.
- Knowledge of System Verilog Assertion and functional coverage.
- Knowledge of code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
- The works involved subsystem level verification that includes test plan writing, writing tests in UVM and System Verilog, debugging RTL issues, coverage writing and SVA, waveform debug using Verdi.
Qualifications
- 2-10+ years and above of experience Digital Design Verification related experience.
- Bachelor or Master's Degree in Computer Science, Computer Engineering, Electrical and Electronics Engineering.
- Strong domain knowledge in one or more PCIe, USB, Ethernet, ARM, Networking, CPU, ARM, Graphics (DDR, PCIe, USB).
- Experience in system interconnect bus and protocol (AXI, AHB, AMBA).
- Good understanding in functional and code coverage.
- Strong in System Verilog and OOP.
- Knowledge in simulation tools like Synopsys VCS and Verdi/DVE.
- Experience in hardware validation and debugging is a plus.
- Proficiency in one scripting language like Perl, Python, Unix, C++ etc.
- Strong communication and analytical skills and ability to work as a team with other groups or different sites.
