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8
Ahb Jobs
Senior SoC Design Engineer
AdoreSys Pte Ltd
Permanent Job
Penang
,
Bayan
,
Malaysia
5-7 years
IO Controller
SOC design
Hardware Emulation
Memory Design
Functional Safety
Design Constraint
Axi
rtl verification
HBM
D2D
CXL
APB Interface
ASIC Design
EDA Tools
AMBA Bus Architecture
AHB
Rtl Design
LPDDR5
DDR
Pcie
Verilog
Ethernet
System Verilog
9 days ago
Design Verification Engineer
Quest Global
Permanent Job
Penang
,
Malaysia
2-10 years
hardware validation
HDL score
Uvm
Verdi/DVE
Synopsys VCS
Axi
AMBA
Surecov
Graphics
AHB
Unix
Usb
Networking
C++
Ovm
Cpu
Pcie
Perl
Ethernet
Debugging
Arm
System Verilog
Python
7 days ago
FPGA Design System Engineer
Infineon Technologies
Permanent Job
Penang
,
Malaysia
0-2 years
QDR-IV
Microchip Libero
AXI-4
system Verilog RTL coding
Siemens Questasim
QDR-II
PCB design tools
AMD-Vivado
AHB
Spi
Verilog
I2c
16 days ago
Associate III - VLSI (IP Design Verification)
UST Global
Permanent Job
Bayan
,
Malaysia
4-6 years
LINT
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Simulators
Vlsi
FinFet
Cadence
Mentor
Microprocessor architecture
FDSOI
Uvm
CMOS
Calibre
Design
Analog Layout
Synthesis
Dft
Physical Verification
VHDL
CDC/RDC
Extraction
PT/Tempus
Processor Hardening
Assembly
Spice
ETS/TK/FS
Verification
Soft / Hard / Mixed Signal IP Design
Physical Design
Floorplan
Synopsys
Clocks
P&R
C
Makefile
Verilog
System Verilog
TCL/TK
FPGA Design
C++
Perl
a month ago
RTL | Digital Design Engineer
Marquee Semiconductor
Permanent Job
Bayan
,
Malaysia
0-2 years
CHI
Mixed signals SoCs
Low-power
UPF
Security
high-performance techniques
Display port
power management
Architecture
Functional safety
SoCs
Clock Domain Crossing (CDC)
Axi
MIPI
Micro-architecture
coherency
Low Power
AHB
Booting/Reset Flow
DDR
Pcie
PERL
Shell scripting
Python
Usb
Nvme
Ethernet
Tcl
a month ago
Associate III - VLSI (Analog Circuit Design)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Simulators
FinFet
Mentor
Uvm
CMOS
Calibre
Analog Layout
Physical Verification
CDC/RDC
Learning Skills
problem-solving skills
PT/Tempus
Communication Skills
Technical Skills
ETS/TK/FS
Floorplan
Analytical Reasoning
Synopsys
LINT
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Attention To Details
Cadence
Microprocessor architecture
FDSOI
Synthesis
Dft
VHDL
Extraction
Processor Hardening
Assembly
design knowledge
Spice
Soft / Hard / Mixed Signal IP Design
Physical Design
Clocks
P&R
C
Makefile
System Verilog
FPGA Design
C++
Verilog
TCL/TK
Perl
a month ago
Associate III - VLSI (STA)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
LINT
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Simulators
Attention To Details
FinFet
Cadence
Mentor
Microprocessor architecture
FDSOI
Uvm
CMOS
Calibre
Analog Layout
Synthesis
Dft
Physical Verification
VHDL
CDC/RDC
Extraction
problem-solving skills
PT/Tempus
Processor Hardening
Communication Skills
Assembly
Spice
ETS/TK/FS
Soft / Hard / Mixed Signal IP Design
Physical Design
Floorplan
Analytical Reasoning
Synopsys
Clocks
P&R
C
Makefile
Verilog
System Verilog
TCL/TK
FPGA Design
C++
Perl
a month ago
Associate III - VLSI (DFT)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Simulators
checklists
scan timing checks
FinFet
Mentor
Uvm
CMOS
Calibre
Analog Layout
Physical Verification
CDC/RDC
problem-solving skills
PT/Tempus
Communication Skills
design life-cycle process
ETS/TK/FS
Floorplan
Analytical Reasoning
Synopsys
LINT
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Attention To Details
Cadence
Microprocessor architecture
FDSOI
Synthesis
Dft
VHDL
Extraction
Validation
Processor Hardening
Assembly
MBIST generation
Spice
Soft / Hard / Mixed Signal IP Design
ATPG test pattern generation
Physical Design
DFT Implementation
Clocks
P&R
C
Makefile
System Verilog
FPGA Design
C++
Verilog
TCL/TK
Templates
Perl
a month ago
1
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