Tcl Jobs

Design Verification Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

UFS CHI Ace Uvm Memory Controller systemverilog AMBA Axi APB C Usb Shell Pcie Perl Python Tcl

4 days ago

Senior Engineer- Test development Engineering

Permanent Job

Batu ,

Penang ,

Malaysia

4-6 years

Statistical Tools NAND microcontroller architectures C/C++ Hardware Flash Technology Uart Spi Software Testers Jtag Design Patterns Pcie I2c Javascript Python Tcl

17 days ago

FEINT Leader

Permanent Job

Bayan ,

Malaysia

3-5 years

ASIC Eda Shell Perl Python Tcl

29 days ago

Applications Engineering, Engineer

Permanent Job

Penang ,

Malaysia

1-3 years

Signoff primetime Fusion Compiler Formality PrimeClosure RTL2GDS PNR EDA Tools scripting skills Functional Verification advanced process nodes Perl Python Tcl

a month ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

RTL | Digital Design Engineer

Permanent Job

Bayan ,

Malaysia

0-2 years

CHI Mixed signals SoCs Low-power UPF Security high-performance techniques Display port power management Architecture Functional safety SoCs Clock Domain Crossing (CDC) Axi MIPI Micro-architecture coherency Low Power AHB Booting/Reset Flow DDR Pcie PERL Shell scripting Python Usb Nvme Ethernet Tcl

30 days ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

30 days ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

30 days ago

Senior SOC Design Engineer

Permanent Job

Bayan ,

Malaysia

5-7 years

cpu design MMU DDR Eda Cache python Perl Verilog Tcl

30 days ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago

Design Enablement Testchip Physical Design Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

physical design methodologies electrical rule checking formal equivalence verification Reliability physical clock design layout verification static and dynamic power integrity Dft EDA Tools product-level parameters Synthesis coverage analysis structural design checking optimizes design Place And Route power and noise analysis flow automation Floor Planning power/clock distribution Timing Closure multiple power domain analysis Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

Design Enablement Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

Design Technology Co-Optimization Si Validation Foundational IPs Digital Computer Science RTL STEM Gds Process Design Kits Electrical Engineering Design Flow Eda Perl Analog Python Computer Engineering Tcl

5 months ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Sta Dc CTS Synopsys implementation tools ICC2 Mentor Verification tool RTL timing optimization physical verification flows Cadence LVS written communication skills Innovus Calibre power grid implementation APR placement advanced process nodes EM Ir Floor Planning Eco TCL coding DRC synopsys primetime GDSII routing Static Timing Analysis Python Perl

5 months ago

E-core CPU Senior Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-8 years

APR flows primetime Noise Fusion Compiler cross-talk ICC2 Conformal Physical Design electro-migration checks Calibre Synthesis Layout physical design Formal equivalence redhawk Dce StarRCXT Ir DRC/LVS OCV analysis Timing Verification Timing Closure DCT ICV Cpu Soc Tcl Scripting

5 months ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Logic Synthesis Reliability RTL physical clock design Physical Design Dft ASIC Gds EDA Tools Structural Design automated place and route tools Synthesis coverage analysis VLSI circuits Place And Route power and noise analysis design techniques Logic equivalent verification debugging sub-micron CMOS technologies Floor Planning power/clock distribution Timing Closure multiple power domain analysis Testchip Logic design fundamentals Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

Development Tools Software Engineer

Permanent Job

Penang ,

Malaysia

2-4 years

Tensor Flow Go Liberty Model Cell Characterization CMOS C++ Postgresql Nodejs Django Javascript Perl MySQL Php MongoDB Keras Ruby Python Tcl

5 months ago

Custom IP Circuit Design Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Layout Design Hspice analog integrated circuit design knowledge analog circuit customization design tools virtuoso CMOS devices Python Tcl

5 months ago

PDK Development Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

layout verification software Layout of analog LVS test-cases development parasitic 2D and 3D electromagnetic packages validation of Process Design Kit (PDK) collaterals Extraction runset and flow development Automation Software Technology file development popular extraction solutions industry standard CAD tools analysis of CAD tool results CAD Custom Layout tools interconnects Digital Circuits rc extraction electromagnetic packages Rf DRC QA plans solvers schematic entry Unix Eda Python Analog Perl Linux Tcl

5 months ago

E-core CPU Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-5 years

5 months ago

AMS Design Flow Engineer

Permanent Job

Penang ,

Malaysia

4-6 years

Skill Physical Verification Physical Design Shell scripting language advanced technology nodes Design Automation CAD layout tools analog design principles layout guidelines Standard Cell Layout Perl Python Tcl

5 months ago

Senior Structural/Physical Design Engineer

Permanent Job

Penang ,

Malaysia

3-4 years

VHDL Vlsi EDA Tools Physical Design Perl Verilog Tcl

5 months ago

E-core CPU Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-5 years

5 months ago

Senior Design Verification Engineer

Permanent Job

Penang ,

Malaysia ,

George Town

0-3 years

Uvm systemverilog Perl Pcie Linux Python Tcl

4 months ago

Senior Backend Physical Verification Engineer Leader

Permanent Job

Penang ,

Malaysia ,

George Town

5-7 years

EDA Tools DRC Antenna EM LVS Physical Verification backend notation Perl Python Tcl

4 months ago

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tcl Jobs

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Tcl Jobs

Design Verification Engineer

Senior Engineer- Test development Engineering

FEINT Leader

Applications Engineering, Engineer

Associate III - VLSI (IP Design Verification)

RTL | Digital Design Engineer

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (STA)

Associate III - VLSI (DFT)

Senior SOC Design Engineer

Physical Design Engineer

Design Enablement Testchip Physical Design Graduate Trainee

Design Enablement Graduate Trainee

Physical Design Engineer

E-core CPU Senior Physical Design Engineer

Physical Design Engineer

Development Tools Software Engineer

Custom IP Circuit Design Engineer

PDK Development Graduate Trainee

E-core CPU Physical Design Engineer

AMS Design Flow Engineer

Senior Structural/Physical Design Engineer

E-core CPU Physical Design Engineer

Senior Design Verification Engineer

Senior Backend Physical Verification Engineer Leader