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Synopsys Jobs in Bayan
Associate III - VLSI (IP Design Verification)
UST Global
Permanent Job
Bayan
,
Malaysia
4-6 years
LINT
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Simulators
Vlsi
FinFet
Cadence
Mentor
Microprocessor architecture
FDSOI
Uvm
CMOS
Calibre
Design
Analog Layout
Synthesis
Dft
Physical Verification
VHDL
CDC/RDC
Extraction
PT/Tempus
Processor Hardening
Assembly
Spice
ETS/TK/FS
Verification
Soft / Hard / Mixed Signal IP Design
Physical Design
Floorplan
Synopsys
Clocks
P&R
C
Makefile
Verilog
System Verilog
TCL/TK
FPGA Design
C++
Perl
a month ago
Associate III - VLSI (Analog Circuit Design)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Simulators
FinFet
Mentor
Uvm
CMOS
Calibre
Analog Layout
Physical Verification
CDC/RDC
Learning Skills
problem-solving skills
PT/Tempus
Communication Skills
Technical Skills
ETS/TK/FS
Floorplan
Analytical Reasoning
Synopsys
LINT
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Attention To Details
Cadence
Microprocessor architecture
FDSOI
Synthesis
Dft
VHDL
Extraction
Processor Hardening
Assembly
design knowledge
Spice
Soft / Hard / Mixed Signal IP Design
Physical Design
Clocks
P&R
C
Makefile
System Verilog
FPGA Design
C++
Verilog
TCL/TK
Perl
a month ago
Associate III - VLSI (STA)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
LINT
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Simulators
Attention To Details
FinFet
Cadence
Mentor
Microprocessor architecture
FDSOI
Uvm
CMOS
Calibre
Analog Layout
Synthesis
Dft
Physical Verification
VHDL
CDC/RDC
Extraction
problem-solving skills
PT/Tempus
Processor Hardening
Communication Skills
Assembly
Spice
ETS/TK/FS
Soft / Hard / Mixed Signal IP Design
Physical Design
Floorplan
Analytical Reasoning
Synopsys
Clocks
P&R
C
Makefile
Verilog
System Verilog
TCL/TK
FPGA Design
C++
Perl
a month ago
Associate III - VLSI (DFT)
UST Global
Permanent Job
Bayan
,
Malaysia
0-2 years
AHB/AXI/PCIe/USB/Ethernet/SPI/I2C
Simulators
checklists
scan timing checks
FinFet
Mentor
Uvm
CMOS
Calibre
Analog Layout
Physical Verification
CDC/RDC
problem-solving skills
PT/Tempus
Communication Skills
design life-cycle process
ETS/TK/FS
Floorplan
Analytical Reasoning
Synopsys
LINT
Circuit Design
Sta
DC/RTL-C
ICC/Innovus/Olympus
Attention To Details
Cadence
Microprocessor architecture
FDSOI
Synthesis
Dft
VHDL
Extraction
Validation
Processor Hardening
Assembly
MBIST generation
Spice
Soft / Hard / Mixed Signal IP Design
ATPG test pattern generation
Physical Design
DFT Implementation
Clocks
P&R
C
Makefile
System Verilog
FPGA Design
C++
Verilog
TCL/TK
Templates
Perl
a month ago
Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)
Celestica
Permanent Job
Penang
,
Bayan
,
Malaysia
0-2 years
Power Distribution
3D passive channel modeling
Electromagnetic
Pcb Design
ANSYS HFSS
Keysight ADS
25G/56G Ethernet specification
Synopsys HSPICE
3-D field solver
ASIC
SerDes channel extraction
S-parameters theory
parallel interfaces
VNA measurements
power integrity analysis
stack-up definition
TDR
Sigrity Power SI
MSEE
Transmission-line
DDR3/4
Mentor ICX
Cst Microwave Studio
multi-gigabit serial links
BSEE
SerDes design
Pcb
Signal Integrity
PCB layout rules
Written Communication
Oral Communication
Cadence SPECCTRAQuest
SiSoft SI-Auditor
SAS
Pcie
Python
VB
Perl
Matlab
a month ago
1
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