Perl Jobs in Bayan

CPU System Validation Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

RTL simulation Ip RISC-V C/C++ Scripting Language Assembly Language Cpu Perl X86 Arm System Verilog Python

4 days ago

Design Verification Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

UFS CHI Ace Uvm Memory Controller systemverilog AMBA Axi APB C Usb Shell Pcie Perl Python Tcl

4 days ago

RTL Logic Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

RTL Sector Analysis Team Circuits Test analytical Tools Languages Problem-solving Channel checkers linting static Verification Timing Digital Independent behaviour cdc Design VHDL collaterals SDC Methodologies Coding Scripting Release Verilog Integration Perl Performance Constraints Routing Python

3 days ago

Embedded Software Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

3-5 years

Yocto Project Linux-based platforms low-level debugging Embedded Systems hardware platform bring-up embedded C/C++ programming Software Development Linux kernel Bash Perl scripting Device Driver Development X86 Application Programming Python Linux Bsp Ui Development

12 days ago

FEINT Leader

Permanent Job

Bayan ,

Malaysia

3-5 years

ASIC Eda Shell Perl Python Tcl

29 days ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

RTL | Digital Design Engineer

Permanent Job

Bayan ,

Malaysia

0-2 years

CHI Mixed signals SoCs Low-power UPF Security high-performance techniques Display port power management Architecture Functional safety SoCs Clock Domain Crossing (CDC) Axi MIPI Micro-architecture coherency Low Power AHB Booting/Reset Flow DDR Pcie PERL Shell scripting Python Usb Nvme Ethernet Tcl

30 days ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

30 days ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

30 days ago

Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

Power Distribution 3D passive channel modeling Electromagnetic Pcb Design ANSYS HFSS Keysight ADS 25G/56G Ethernet specification Synopsys HSPICE 3-D field solver ASIC SerDes channel extraction S-parameters theory parallel interfaces VNA measurements power integrity analysis stack-up definition TDR Sigrity Power SI MSEE Transmission-line DDR3/4 Mentor ICX Cst Microwave Studio multi-gigabit serial links BSEE SerDes design Pcb Signal Integrity PCB layout rules Written Communication Oral Communication Cadence SPECCTRAQuest SiSoft SI-Auditor SAS Pcie Python VB Perl Matlab

a month ago

Senior SOC Design Engineer

Permanent Job

Bayan ,

Malaysia

5-7 years

cpu design MMU DDR Eda Cache python Perl Verilog Tcl

30 days ago

Senior Software Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

3-8 years

C/C++ TETRA Sensors artificial intelligent (AI WiFi C# automation Nfc Machine Learning Lte Ble Bash Python Perl Assembly Language Linux Kernel

5 months ago

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Perl Jobs in Bayan

CPU System Validation Engineer

Design Verification Engineer

RTL Logic Design Engineer

Embedded Software Engineer

FEINT Leader

Associate III - VLSI (IP Design Verification)

RTL | Digital Design Engineer

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (STA)

Associate III - VLSI (DFT)

Signal Integrity/ Power Integrity Engineer (Staff/Senior Staff)

Senior SOC Design Engineer

Senior Software Engineer