Fresher Design Verification Jobs in Penang

Senior Design Verification Engineer

Permanent Job

Penang ,

Malaysia ,

George Town

0-3 years

Uvm systemverilog Perl Pcie Linux Python Tcl

4 months ago

RTL Logic Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

RTL Sector Analysis Team Circuits Test analytical Tools Languages Problem-solving Channel checkers linting static Verification Timing Digital Independent behaviour cdc Design VHDL collaterals SDC Methodologies Coding Scripting Release Verilog Integration Perl Performance Constraints Routing Python

4 days ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago

Design Enablement Testchip Physical Design Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

physical design methodologies electrical rule checking formal equivalence verification Reliability physical clock design layout verification static and dynamic power integrity Dft EDA Tools product-level parameters Synthesis coverage analysis structural design checking optimizes design Place And Route power and noise analysis flow automation Floor Planning power/clock distribution Timing Closure multiple power domain analysis Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

E-core CPU Senior Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-8 years

APR flows primetime Noise Fusion Compiler cross-talk ICC2 Conformal Physical Design electro-migration checks Calibre Synthesis Layout physical design Formal equivalence redhawk Dce StarRCXT Ir DRC/LVS OCV analysis Timing Verification Timing Closure DCT ICV Cpu Soc Tcl Scripting

5 months ago

PDK Development Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

layout verification software Layout of analog LVS test-cases development parasitic 2D and 3D electromagnetic packages validation of Process Design Kit (PDK) collaterals Extraction runset and flow development Automation Software Technology file development popular extraction solutions industry standard CAD tools analysis of CAD tool results CAD Custom Layout tools interconnects Digital Circuits rc extraction electromagnetic packages Rf DRC QA plans solvers schematic entry Unix Eda Python Analog Perl Linux Tcl

5 months ago

E-core CPU Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-5 years

5 months ago

E-core CPU Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-5 years

5 months ago

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Fresher Design Verification Jobs in Penang

Senior Design Verification Engineer

RTL Logic Design Engineer

Physical Design Engineer

Design Enablement Testchip Physical Design Graduate Trainee

E-core CPU Senior Physical Design Engineer

PDK Development Graduate Trainee

E-core CPU Physical Design Engineer

E-core CPU Physical Design Engineer