Fresher Circuit Analysis Jobs

Analog Layout Designer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

Mentor Calibre DRC/LVS/ERC Circuit schematic-driven layout chip level routing Independent design rule Trouble Shooting high-speed signals layout techniques critical device matching CAD Tools Analysis self-motivated Floor Planning Responsibility urgency physical design verifications mixed-signal Team Spirit creative problem solver Analog

4 days ago

Engineer II - Electronics

Permanent Job

Penang ,

Malaysia

0-2 years

magnetic design measurement systems parallel switch networks VCO AC power factor correction Spc inductor Component Life Cycle Analysis rectifiers ISO system 6 sigma methodologies Parts Universe Part Miner high power transistors DC circuits Puma Digital AC to DC converters DC current measurement SMPS Switch Mode Power Supply topology LCC resonant circuit analog loop stability worse case component analysis Test V/I sensors Promiere Troubleshooting series electrical/safety regulatory compliance transformer concepts enterprise resource planning tools SAP Ihs Firmware

13 days ago

Test Development Engineer (Open for fresh graduates)

Permanent Job

Penang ,

Malaysia

0-2 years

Digital Debug Semiconductor ATE software development Circuit Simulation PCB layout software CMOS digital logic Measurement Systems Analysis schematic diagrams CAD Software C# C C++ Analog

21 days ago

Sr Engineer, NVE PE

Permanent Job

Batu ,

Penang

0-2 years

CMOS Reliability Simulation Electrical Problem Solving Analysis CMOS Circuit Design Physics CAD NAND Component electronic engineering Communication Testing System Architecture Debugging

24 days ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago