Floor Planning Jobs in Penang

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

1-3 years

electrical rule checking formal equivalence verification Reliability physical clock design layout verification Physical Design placing static and dynamic power integrity Dft EDA Tools Synthesis coverage analysis VLSI circuits structural design checking Place And Route power and noise analysis design techniques logic equivalent verification debugging logic design fundamentals sub-micron CMOS technologies Logic Synthesis Floor Planning reliability verification power/clock distribution Timing Closure multiple power domain analysis scripting skills Clock Tree Synthesis static timing analysis routing Python Programming Language Perl Tcl

5 hours ago

SoC Physical Design Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Noise Pv Clock Tree Designs Signal Integrity Lv power optimization Dfm RC-extraction Synthesis Floor Planning DRC FEV Power-grid Place And Route Eda Rv Static Timing Analysis

9 days ago

SoC Physical Design Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

Sta Cross Functional Stakeholders RC-Extraction Noise Clock Tree Design Pv Signal Integrity Lv Power Grid power optimization design methodology Dfm Synthesis technical consultation PNR Floor Planning DRC FEV Industrial EDA Tools Design Trade-off Eda Rv

9 days ago

Analog Layout Designer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

Mentor Calibre DRC/LVS/ERC Circuit schematic-driven layout chip level routing Independent design rule Trouble Shooting high-speed signals layout techniques critical device matching CAD Tools Analysis self-motivated Floor Planning Responsibility urgency physical design verifications mixed-signal Team Spirit creative problem solver Analog

8 days ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

0-2 years

FinFET ICC2 RTL Synopsys Fusion Compiler circuit/logic simulation Optimization STA signoff Block P&R Physical Verification architecture Dual Patterning nodes tools for logic synthesis Apache Redhawk floorplanning Versatility with scripts to automate design flow physical/timing/electrical quality Place And Route familiarity with tools for schematics Layout automated synthesis establishing design methodology Pd scan stitching feed-thru planning Identify complex technical problems checks for logic equivalence Floorplan Clock Tree Synthesis computer organization high speed datapath Design Compiler primetime final signoff for large IP delivery IP integration Cadence Genus Innovus Synthesis Gds StarRC Placement clock and power gating techniques Full Chip Level Floor planning Clock Tree Synthesis design checks for physical and electrical quality Bus / Pin Planning Mentor Graphics Calibre Timing Analysis Parasitic Extraction design cycle time reduction drive and hands-on flow development and scripting Physical Design timing driven place and route design optimization control logic applications PNR tools perl Static Timing Analysis Routing Unix Python clocking Constraints Shell Linux Tcl

a month ago

Design Enablement Testchip Physical Design Graduate Trainee

Permanent Job

Penang ,

Malaysia

0-2 years

physical design methodologies electrical rule checking formal equivalence verification Reliability physical clock design layout verification static and dynamic power integrity Dft EDA Tools product-level parameters Synthesis coverage analysis structural design checking optimizes design Place And Route power and noise analysis flow automation Floor Planning power/clock distribution Timing Closure multiple power domain analysis Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

Physical Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Logic Synthesis Reliability RTL physical clock design Physical Design Dft ASIC Gds EDA Tools Structural Design automated place and route tools Synthesis coverage analysis VLSI circuits Place And Route power and noise analysis design techniques Logic equivalent verification debugging sub-micron CMOS technologies Floor Planning power/clock distribution Timing Closure multiple power domain analysis Testchip Logic design fundamentals Clock Tree Synthesis static timing analysis Python Perl Tcl

5 months ago

Analog Design Engineer

Permanent Job

Penang ,

Malaysia

1-3 years

Analog Design voltage regulators Xtal oscillator buffers op-amps digital-analog mixed signal circuits buffers spice simulation Circuit Design high speed frequency dividers layout floor-planning Sensors area/power reduction bias references standard cells

5 months ago

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Floor Planning Jobs in Penang

Physical Design Engineer

SoC Physical Design Engineer

SoC Physical Design Engineer

Analog Layout Designer

Physical Design Engineer

Design Enablement Testchip Physical Design Graduate Trainee

Physical Design Engineer

Analog Design Engineer