Design Verification Jobs

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

2-10 years

hardware validation HDL score Uvm Verdi/DVE Synopsys VCS Axi AMBA Surecov Graphics AHB Unix Usb Networking C++ Ovm Cpu Pcie Perl Ethernet Debugging Arm System Verilog Python

4 days ago

Design Verification Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

7-9 years

UFS CHI Ace Uvm Memory Controller systemverilog AMBA Axi APB C Usb Shell Pcie Perl Python Tcl

4 days ago

Senior Design Verification Engineer

Permanent Job

Malaysia ,

Kuala Lumpur

3-5 years

Usb Pcie

12 days ago

Associate III - VLSI (IP Design Verification)

Permanent Job

Bayan ,

Malaysia

4-6 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Vlsi FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Design Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction PT/Tempus Processor Hardening Assembly Spice ETS/TK/FS Verification Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Design Verification Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

4-15 years

Axi SV Uvm Usb Pcie Debugging

a month ago

Senior Mechanical Engineer

Permanent Job

Malaysia ,

Kuala Lumpur

8-15 years

offshore facilities Design Verification Fabrication single-discipline check energy transition Design Calculations inter-discipline check subsea infrastructure design codes Oil And Gas onshore landscape procurement engineering disciplines design reports Mechanical Engineering offshore wind infrastructure Technical Specifications FEED Studies

11 days ago

Design Verification Director

Permanent Job

Penang ,

Malaysia

20-22 years

HW/FW interaction verification low power design multi-instance VIPs UVM methodology SOC level FPGA designs AMBA bus architecture Perl/Python/Tcl SOC designs UVM based highly reusable test benches C/C++ UPF integration Firmware System Verilog

3 months ago

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Debug Uvm systemverilog digital simulation assembly DDR protocols C/C++ Noc Cpu Perl Pcie Verilog Ethernet Python

5 months ago

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

hardware validation Debug Simulation Tools make PCIE protocols ASIC C/C++ Fpga Soc Shell Scripting Perl Python Tcl

5 months ago

Design Verification Engineer

Permanent Job

Penang ,

Malaysia

3-5 years

hardware validation Debug Simulation Tools make PCIE protocols ASIC C/C++ Fpga Soc Shell Scripting Perl Python Tcl

5 months ago

Senior Design Verification Engineer

Permanent Job

Penang ,

Malaysia ,

George Town

0-3 years

Uvm systemverilog Perl Pcie Linux Python Tcl

4 months ago

PCB Engineer

Permanent Job

Penang ,

Malaysia

1-2 years

Circuit Analysis Dfm Design Verification IPC standards DFF PADs software Dft Simulation

27 days ago

Principal Naval Architect

Permanent Job

Malaysia ,

Kuala Lumpur

15-20 years

project specifications Transportation analysis installation engineering Document Control Design Calculations Marine customers project management team technical queries installation equipment EPCIC Offshore Platforms resource requirements technical quality audit reviews Deviation single-discipline check performance evaluation classification society engineering/analysis marine warranty surveyor Design Verification offloading analysis upending analysis subcontractors and vendors weather design reports vendor and subcontractor submittals weight report QC and certification group structural eng Naval Architecture lessons learned Fabrication project cost controller mooring analysis inter-discipline check subsea infrastructure Floatover Engineering Standards installation loads Dynamic Jacket Launch design codes lead role project planner Jacket/topside loadout procurement offshore wind infrastructure clash-free designs FEED

a month ago

Hardware Engineer

Permanent Job

Malaysia ,

Kulai

1-3 years

Digital Word project management multi-tasking fast-paced environment Team Player radio frequency Pcb Circuit Design design verification test Testing Ms Office Analog Excel

30 days ago

Sr. Engineer/ Asst. Staff Engineer- Verification & Validation

Permanent Job

Penang ,

Bayan ,

Malaysia

4-6 years

product design control Fda test method validation product reliability test product design verification root-caused analysis Validation ISO13485 Statistical Analysis

5 months ago

Senior SoC Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

5-7 years

IO Controller SOC design Hardware Emulation Memory Design Functional Safety Design Constraint Axi rtl verification HBM D2D CXL APB Interface ASIC Design EDA Tools AMBA Bus Architecture AHB Rtl Design LPDDR5 DDR Pcie Verilog Ethernet System Verilog

5 days ago

RTL Logic Design Engineer

Permanent Job

Penang ,

Bayan ,

Malaysia

0-2 years

RTL Sector Analysis Team Circuits Test analytical Tools Languages Problem-solving Channel checkers linting static Verification Timing Digital Independent behaviour cdc Design VHDL collaterals SDC Methodologies Coding Scripting Release Verilog Integration Perl Performance Constraints Routing Python

3 days ago

Staff Electronic Hardware Design Engineer

Permanent Job

Perai ,

Malaysia

5-10 years

EDA Tools hardware platform Decision Making Verbal Communication mentor junior engineers design documentation Schematics Problem Solving BOMs cross-functional team environment embedded hardware architecture design Pcb Layout costing studies design FMEA Written Communication product verification

12 days ago

Staff/ Senior SOC Design Engineer

Permanent Job

Penang ,

Malaysia

5-7 years

Synthesis RTL digital circuit design script language clock/reset structure Verification peripheral IO timing signoff SDIO micro-architectures Eda Uart Soc Spi Verilog

17 days ago

Analog Design Engineer

Permanent Job

Malaysia ,

Kuching ,

Sarawak

5-7 years

device parasitics stability analysis analog block designs written and oral communications skills Technical CMOS process Cadence noise analysis LDO regulators feedback analysis Responsibility EDA Tools Siemens VCOs design rules Comparators 6-sigma design practices DRC/LVS/ERC engineering tasks verification procedures Simulation Models solution driven self-motivated English Amplifiers bandgap voltage references Synopsys Verilog A/AMS modelling Statistical Analysis

28 days ago

Senior Contract Executive (ID & Fit Out)

Permanent Job

Malaysia

4-6 years

BQ Commercial Sub-contractor/supplier payment verification Progress payment Quantity Surveying Site work evaluation Interior Design

30 days ago

Senior Contract Executive/ Contract Executive (ID & Fit Out)

Permanent Job

Malaysia

4-6 years

BQ Commercial Sub-contractor/supplier payment verification Progress payment Quantity Surveying Site work evaluation Interior Design

30 days ago

Associate III - VLSI (Analog Circuit Design)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC Learning Skills problem-solving skills PT/Tempus Communication Skills Technical Skills ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Processor Hardening Assembly design knowledge Spice Soft / Hard / Mixed Signal IP Design Physical Design Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Perl

30 days ago

Associate III - VLSI (STA)

Permanent Job

Bayan ,

Malaysia

0-2 years

LINT AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Simulators Attention To Details FinFet Cadence Mentor Microprocessor architecture FDSOI Uvm CMOS Calibre Analog Layout Synthesis Dft Physical Verification VHDL CDC/RDC Extraction problem-solving skills PT/Tempus Processor Hardening Communication Skills Assembly Spice ETS/TK/FS Soft / Hard / Mixed Signal IP Design Physical Design Floorplan Analytical Reasoning Synopsys Clocks P&R C Makefile Verilog System Verilog TCL/TK FPGA Design C++ Perl

30 days ago

Associate III - VLSI (DFT)

Permanent Job

Bayan ,

Malaysia

0-2 years

AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Simulators checklists scan timing checks FinFet Mentor Uvm CMOS Calibre Analog Layout Physical Verification CDC/RDC problem-solving skills PT/Tempus Communication Skills design life-cycle process ETS/TK/FS Floorplan Analytical Reasoning Synopsys LINT Circuit Design Sta DC/RTL-C ICC/Innovus/Olympus Attention To Details Cadence Microprocessor architecture FDSOI Synthesis Dft VHDL Extraction Validation Processor Hardening Assembly MBIST generation Spice Soft / Hard / Mixed Signal IP Design ATPG test pattern generation Physical Design DFT Implementation Clocks P&R C Makefile System Verilog FPGA Design C++ Verilog TCL/TK Templates Perl

30 days ago

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Design Verification Jobs

Design Verification Engineer

Design Verification Engineer

Senior Design Verification Engineer

Associate III - VLSI (IP Design Verification)

Design Verification Engineer

Senior Mechanical Engineer

Design Verification Director

Design Verification Engineer

Design Verification Engineer

Design Verification Engineer

Senior Design Verification Engineer

PCB Engineer

Principal Naval Architect

Hardware Engineer

Sr. Engineer/ Asst. Staff Engineer- Verification & Validation

Senior SoC Design Engineer

RTL Logic Design Engineer

Staff Electronic Hardware Design Engineer

Staff/ Senior SOC Design Engineer

Analog Design Engineer

Senior Contract Executive (ID & Fit Out)

Senior Contract Executive/ Contract Executive (ID & Fit Out)

Associate III - VLSI (Analog Circuit Design)

Associate III - VLSI (STA)

Associate III - VLSI (DFT)